1. Field of the Invention
The present invention relates generally to buffer amplifiers, and more particularly, to methods and systems for dynamically optimizing an I/O receiver performance for the current, local temperature of the I/O receiver.
2. Description of the Related Art
Integrated circuits (ICs) typically have thermal gradients across the IC. The thermal gradients are typically caused by different functions being carried out in one portion of the IC than in another portion of the IC because the different functions can lead to variations in power dissipation across the IC. FIG. 1A shows a temperature gradient across a typical microprocessor die 100. The hottest area 102 can have a relatively high operating temperature such as about 105 degrees C. or higher. An adjacent area 104 is slightly cooler at approximately 80 degrees C. An even cooler area 106 is approximately 50 degrees C. The remaining area 108 is approximately 20 degrees C.
The hottest area 102 can include portions of the core processor unit, which perform functions nearly every clock cycle. By comparison, some of the ancillary portions of the microprocessor die 100, such as memory registers and other, non-core functions, operate at cooler temperatures because these ancillary portions may not perform a function every clock cycle or for other reasons described below. As a result, these ancillary portions are typically cooler areas of the microprocessor die 100.
Some portions of the microprocessor die 100 may also have higher device densities than other portions of the microprocessor die 100. The higher density portions, such as the processing core, would typically have a higher temperature than less dense areas 104, 106, 108, because more operations and current flow occurs in higher device density areas. Therefore a temperature gradient can often result between the different areas 102, 104, 106, 108 of the microprocessor die 100.
Temperature variations (i.e., gradients) between different I/O receivers can cause the different I/O receivers to switch at different times. As a result, the outputs of the different I/O receivers do not switch at the same time and therefore a longer sampling time (i.e., delay) is required to accurately collect the output data from all of the I/O receivers. The longer sampling delay reduces the total data throughput from all of the I/O receivers.
Amplifiers such as I/O receivers and others are typically constructed from MOS transistors (NMOS and PMOS). The current flow, Id through a saturated MOS transistor can determined by the following Relationship 1:Id=1/2*u*Cox*W/L*(Vgs−Vt)2  Relationship 1                 u is the mobility of electrons in NMOS (or holes in PMOS). Cox is the gate electrode capacitance. W/L are the physical dimensions of the device. Vgs is the gate-source voltage applied across the gate-source junction. Vt is equal to bias voltage as will be described below. Vt is the turn-on, or threshold voltage. By way of example, as temperature goes up, the mobility parameter will shift according to the following Relationship 2:u=uo(300/T)3/2  Relationship 2         uo is the mobility of electrons (or holes) @ 300 Kelvin. As T goes up, u goes down. Also as u goes down, physically larger device dimensions (W/L) are required to maintain the same level of current as shown above in Relationship 1. However, when larger devices are used, the relative current must be increased even more due to the additional capacitance resulting from the physically larger devices. Capacitance is typically proportional to physical area of the devices.        
The time required for an amplifier such as a I/O receiver to switch (i.e., switching time (ΔT)) is defined by the following Relationship 3:ΔV=(I*ΔT)/C  Relationship 3 
Where ΔV is the change in voltage across the capacitance C of a node and I is a charging or discharging current across the capacitance C. As shown in Relationship 3 above, the switching time is proportional to the capacitance of the node or device junction in the amplifier. Therefore, as the capacitance increases the switching time also increases.
As described above in FIG. 1A and Relationships 1-3, temperature variations (i.e., gradients) between different I/O receivers can cause the different I/O receivers to switch at different times. By way of example, FIG. 1B shows a typical multi-bit bus 120 connected to the microprocessor die 100. The multi-bit bus 120 is a 64-bit bus and includes 64 different bit lines 122A-122LLL. Each of the bit lines 122A-122LLL has a dedicated I/O receiver 124A-124LLL. A significant temperature gradient can occur across the 64 I/O receivers 124A-124LLL. The 64-bit bus 120 also includes a single clock signal 128 that is used to synchronize the data sampling from each of the 64 bit lines 122A-122LLL. The clock signal 128 is delayed 90-degrees in a clock delay circuit 130. The 90-degree delayed clock signal is coupled to the sample and hold circuits 126A-126LLL.
FIG. 1C is a timing diagram 150 of the clock signal 128 and the data signals on bit lines 122A, 122LLL. Typically, the clock signal 128 is delayed 90-degrees so as to maximize the probability of detecting the desired data signal on each I/O receiver 124A-124LLL. Simply put, the 90-degree delayed clock signal provides each I/O receiver 124A-124LLL a 90-degree timeframe to detect the respective data signal 122A-122LLL and switch the output of the I/O receiver 124A-124LLL according to the corresponding detected data signal 122A-122LLL.
As shown in FIG. 1C, a temperature gradient across the 64 I/O receivers 124A-124LLL can delay the 64 separate data signals 122A-122LLL varying amounts such as 30-degrees delayed in I/O receiver 122A and 40 degrees advanced in I/O receiver 122LLL. The 90-degree delayed clock signal 132 allows the correct signal from each of the bit streams 122A, 122LLL to be accurately detected at time T1. Conversely at time T0, the data signal 122A has not yet switched as the data signal 122A is delayed 30-degrees due to a temperature gradient. As a result, the total data throughput (bit rate) of the 64-bit bus 120 is reduced because additional time is required to accurately resolve each data bit. What is needed is a method and system for correcting each I/O receiver 124A-124LLL according to the local temperature of each I/O receiver 124A-124LLL so as to equalize all propagation delays or advances in the I/O receivers 124A-124LLL.
Designing all I/O receivers to operate at 105 degrees C. when not all of the I/O receivers will actually operate at 105 degrees C. will unnecessarily increase the size of the devices required, increase the internal node capacitances leading to increased switching time. Further, the larger physical device sizes of the I/O receivers designed to operate at 105 degrees C. limit the possible locations of the I/O receivers.
Another problem specific to some ICs, such as a microprocessor and other processor-type ICs is that depending upon the actual function being performed, the temperature gradients may migrate around the IC. For example, a first portion of the IC may be very hot when performing a first function. Alternatively, when the IC is performing second function, the first portion may be substantially cooler because another portion of the IC is performing the bulk of the second function. Therefore, it is not efficient to design I/O receivers in a first portion of the IC to be optimized for operating at 20 degrees C. and I/O receivers in a second portion of the IC to be optimized for operating at 105 degrees C. when the actual operating temperatures of each portion of the IC can vary significantly.
Further still, as device densities have increased, the temperature gradients have similarly increased. By way of example, some current generations of ICs have temperature gradients as much as 50 degrees C. or more across the IC. In one current generation CPU the operating temperature can be 105 degrees C. or hotter in the hotter portions of the CPU and 50 degrees C. or less in the “cooler” portions of the CPU. Designing I/O receivers throughout the entire CPU to operate at 105 degrees C. is very inefficient use of power and also results in slower switching (i.e., lower speed) I/O receivers, which degrades overall CPU performance as described above.
In view of the foregoing, there is a need for a system and method for adjusting the amplification control parameters for each I/O receiver I/O receiver according to the local thermal characteristics of the I/O receiver.